Cargando…

RISC without RISK?: an overview of current RISC computers in use in HEP batch

Detalles Bibliográficos
Autor principal:	Jarp, S
Lenguaje:	eng
Publicado:	CERN 1992
Materias:	Computing and Computers
Acceso en línea:	https://dx.doi.org/10.5170/CERN-1992-007.499 http://cds.cern.ch/record/242401

Ejemplares similares

Performance awareness: execution performance of HEP codes on RISC platforms,issues and solutions
por: Yaari, R, et al.
Publicado: (1995)

MMIXware: a RISC computer for the third Millennium
por: Knuth, Donald Ervin
Publicado: (1999)

Microprocessor architectures: RISC, CISC and DSP
por: Heath, Steve
Publicado: (1995)

High Performance CISC, RISC and VLIW Processors
por: Rao, G S
Publicado: (1992)

A blocked implementation of level 3 BLAS for RISC processors
por: Daydé, M J, et al.
Publicado: (1996)

Mainframe services using RISC-based workstations: the first two years' experience at CERN
por: Hemmer, F, et al.
Publicado: (1992)

Vlsi chip design with the hardware description language VERILOG: an introduction based on a large RISC processor design
por: Golze, Ulrich, et al.
Publicado: (1996)

Predicting Hospitalised Paediatric Pneumonia Mortality Risk: An External Validation of RISC and mRISC, and Local Tool Development (RISC-Malawi) from Malawi
por: Hooli, Shubhada, et al.
Publicado: (2016)

Correction: Predicting Hospitalised Paediatric Pneumonia Mortality Risk: An External Validation of RISC and mRISC, and Local Tool Development (RISC-Malawi) from Malawi
por: Hooli, Shubhada, et al.
Publicado: (2018)

Validity and reliability of the German versions of the CD-RISC-10 and CD-RISC-2
por: Wollny, Anna Irena, et al.
Publicado: (2021)

Microprocesadores RISC : evolución y tendencias /
Publicado: (2000)

The future of commodity computing and many-core versus the interests of HEP software
por: Jarp, Sverre, et al.
Publicado: (2012)

RISC Technology and workstations report
Publicado: (1992)

AVR RISC microcontrollers handbook /
por: Kühnel, Claus, 1951-
Publicado: (1998)

External validation of the RISC, RISC-Malawi, and PERCH clinical prediction rules to identify risk of death in children hospitalized with pneumonia
por: Rees, Chris A, et al.
Publicado: (2021)

Beyond core count: a look at new mainstream computing platforms for HEP workloads
por: Szostek, Pawel, et al.
Publicado: (2014)

Clarifying mammalian RISC assembly in vitro
por: Tan, Grace S, et al.
Publicado: (2011)

Diced Triplets Expose Neurons to RISC
por: Rudnicki, Dobrila D., et al.
Publicado: (2012)

Small Molecule Inhibition of RISC Loading
por: Tan, Grace S., et al.
Publicado: (2011)

Taking the RISC of exiting naïve pluripotency
por: Guallar, Diana, et al.
Publicado: (2016)

Evaluating the scalability of HEP software and multi-core hardware
por: Jarp, S, et al.
Publicado: (2011)

Many-core experience with HEP software at CERN openlab
por: Jarp, Sverre, et al.
Publicado: (2012)

RISC Architecture Microprocessor Farm for offline analysis
por: De Barros, C, et al.
Publicado: (1992)

A Practitioner's guide to Risc microprocessor architecture
por: Stakem, Patrick H.
Publicado: (1996)

Physical Activity and Insulin Sensitivity: The RISC Study
por: Balkau, Beverley, et al.
Publicado: (2008)

Intracytoplasmic Re-localization of miRISC Complexes
por: Akgül, Bünyamin, et al.
Publicado: (2018)

RISC-interacting clearing 3’- 5’ exoribonucleases (RICEs) degrade uridylated cleavage fragments to maintain functional RISC in Arabidopsis thaliana
por: Zhang, Zhonghui, et al.
Publicado: (2017)

Experience with low-power x86 processors (Atom) for HEP usage. An initial analysis of the Intel® dual core Atom™ N330 processor
por: Balazs, G, et al.
Publicado: (2009)

POSIX realtime extension and RISC/UNIX data acquisition
por: Yasu, Y, et al.
Publicado: (1992)

Building a RISC-V CPU in 5 minutes
por: Devine, James
Publicado: (2019)

A useful approach to total analysis of RISC-associated RNA
por: Hayashida, Yukinobu, et al.
Publicado: (2009)

Does the Intel Xeon Phi processor fit HEP workloads?
por: Nowak, Andrzej, et al.
Publicado: (2014)

Age-dependent patterns of microRNA RISC loading
por: Grigoriev, Andrey, et al.
Publicado: (2014)

In vitro reconstitution of chaperone-mediated human RISC assembly
por: Naruse, Ken, et al.
Publicado: (2018)

ECC Memory for Fault Tolerant RISC-V Processors
por: Dörflinger, Alexander, et al.
Publicado: (2020)

The Role of Dynamic miRISC During Neuronal Development
por: Nawalpuri, Bharti, et al.
Publicado: (2020)

Modulation of miRISC-Mediated Gene Silencing in Eukaryotes
por: Jungers, Courtney F., et al.
Publicado: (2022)

Benchmarking computers for HEP
por: McIntosh, E
Publicado: (1993)

Trends in computing for HEP
por: Zanella, Paolo
Publicado: (1986)

A review of Japan and Japanese high-end computers
por: Jarp, S
Publicado: (1991)

Cannot write session to /tmp/vufind_sessions/sess_b3hogk5bhncom8vo4iiuu49nck