Cargando…
RISC without RISK?: an overview of current RISC computers in use in HEP batch
Autor principal: | Jarp, S |
---|---|
Lenguaje: | eng |
Publicado: |
CERN
1992
|
Materias: | |
Acceso en línea: | https://dx.doi.org/10.5170/CERN-1992-007.499 http://cds.cern.ch/record/242401 |
Ejemplares similares
-
Performance awareness: execution performance of HEP codes on RISC platforms,issues and solutions
por: Yaari, R, et al.
Publicado: (1995) -
MMIXware: a RISC computer for the third Millennium
por: Knuth, Donald Ervin
Publicado: (1999) -
Microprocessor architectures: RISC, CISC and DSP
por: Heath, Steve
Publicado: (1995) -
High Performance CISC, RISC and VLIW Processors
por: Rao, G S
Publicado: (1992) -
A blocked implementation of level 3 BLAS for RISC processors
por: Daydé, M J, et al.
Publicado: (1996)