A Generic, Modular and User Transparent Protocol Scheme for Inter-FPGA Communication using Serial Links

CERN, the European Organization for Nuclear Research, is a European research organization that operates the largest particle physics laboratory in the world. A large amount of particle accelerators and detectors are developed and used for scientific research purposes. With those, a large amount of information is created and needs to be stored before it can be analysed. As a consequence, the communication reliability, integrity, latency and transfer rates between these detectors and the control room are some of the key elements for the success of those experiments. While it is true that existing communication standards, or protocols, are focused on those key elements, it is usually a balanced compromise to stay polyvalent, where the emphasis on a specific aspect reduces the efficiency of the others. To improve the performance and capabilities of one of the operational accelerator instrument called the beam wire scanner (BWS), the CERN instrumentation Group (BE-BI) has created a complete new electro-mechanical system that will in time replace the current one. This new scanner also has a complete new control and acquisition concept that will require an update of the current communication architecture, mainly because the mechanical and acquisition parts are now split into two distinct elements. This thesis analyses the new demands and challenges for this new communication architecture and implement a point-to-point communication protocol on an optical link, linking the two Field-programmable gate arrays (FPGA) present on both elements of the sub-system (at the speed of 4.8 Gb/s). This protocol needs to satisfy all the new technical aspects, be transparent for the different types of information transiting through it as well as being generic and modular, to facilitate its implementation into other instruments or detectors present at CERN. The protocol designed and developed during this thesis is successful in managing the integrity, latency and transfer rates required, by implementing retransmission mechanisms upon bad data reception and a weighted bandwidth arbiter to deal with latency and transfer rates issues. Furthermore, multiple type of information coming from different services can be transmitted or received in a complete independent and transparent way, thanks to the modularity and generic aspect of the code. A simulation test bench (TB) was also created to verify the reliability of the designed protocol, providing multiple corner case scenarios. Finally, the first physical tests made between two standalone FPGA development boards were a success, making the protocol ready for further integration and tests with application specific FPGA designs.