Design of the ATLAS Phase-II hardware-based tracking processor

The expected increase in peak luminosity of the upgraded high-luminosity LHC will force the ATLAS experiment to increase early stage trigger selection power. The agreed strategy is to implement precise hardware track reconstruction, through which sharper trigger turn-on curves can be achieved for primary single-lepton selections, while contributing to b-tagging and tau-tagging techniques as well as multi-jet rejection. The hardware-based tracking for the trigger (HTT) will use a combination of Associative Memory ASICs and FPGAs to provide the software-based trigger system with access to tracking information. In this poster, we present the requirements, architecture and projected performance of the system in terms of tracking capability, and trigger selection, based on detailed simulations.