FATALIC: a fully integrated electronics readout for the ATLAS tile calorimeter at the HL-LHC

The ATLAS Collaboration has started a vast program of upgrades in the context of high-luminosity LHC (HL-LHC) foreseen in 2024. The current readout electronics of every sub-detector, including the Tile Calorimeter (TileCal), must be upgraded to comply with the extreme HL-LHC operating conditions. The ASIC described in this document, named Front-end ATlAs tiLe Integrated Circuit (FATALIC), has been developed to fulfill these requirements. FATALIC is based on a $130\,$nm CMOS technology and performs the complete processing of the signal, including amplification, shaping and digitization on a large dynamic range from $25\,$fC to $1.2\,$nC. The overall architecture of this current-reading ASIC is composed by current conveyors, shapers, 12-bits pipeline analog-to-digital converters operating at $40\,$Mhz and a digital block dealing with the three gains implemented in this electronics. A dedicated channel for low current is also designed in order to be able to perform absolute calibration with radioactive cesium source, producing a known but low signal with a typical frequency of $100\,$Hz. In this poster, we propose to describe the measured performances of FATALIC and the signal energy and time reconstruction. In addition, tests in real conditions using beam of particles at CERN and measurements of observable of interest, such as the calorimeter response or muon energy loss, with FATALIC will be discussed.