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Design of the ATLAS phase-II hardware-based tracking processor

The expected factor four increase in peak luminosity of the high-luminosity LHC (HL-LHC) compared to the current system will force the ATLAS experiment to increase early stage trigger selection power. The agreed strategy is to implement precise hardware track reconstruction, through which sharper tr...

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Detalles Bibliográficos
Autor principal: Poggi, Riccardo
Lenguaje:eng
Publicado: 2018
Materias:
Acceso en línea:https://dx.doi.org/10.1016/j.nima.2018.11.055
http://cds.cern.ch/record/2626940
Descripción
Sumario:The expected factor four increase in peak luminosity of the high-luminosity LHC (HL-LHC) compared to the current system will force the ATLAS experiment to increase early stage trigger selection power. The agreed strategy is to implement precise hardware track reconstruction, through which sharper trigger turn-on curves can be achieved for primary single-lepton selections, while contributing to b-tagging and tau-tagging techniques as well as pileup mitigation for hadronic signatures, such as multijet and missing transverse momentum. This work discusses the requirements, architecture and projected performance of the system in terms of tracking capability, and trigger selection, based on detailed simulations.