An updated design of the read out link and control board for the Phase-2 upgrade of the ATLAS Tile Calorimeter.

The ATLAS hadronic Tile Calorimeter (TileCal) is being upgraded for the High Luminosity Large Hadron Collider (HL-LHC) that will have a peak luminosity of $5\times10^34$ $cm^{−2} s^{−2}$, five times higher than the design luminosity of the LHC. Following the R&D of the new on-detector electronics, we present a redesign of the read out link and control board, so called Daughterboard (DB). The upgraded system will include 1024 DBs that will serve 12 photomultiplier (PMT) channels each, while handling the control and communication between the front-end and off-detector electronics. The DB provides continuous high-speed readout of two gains of digitized PMT data samples to the off-detector, while receiving configuration, control and timing that distributes to the front-end, all over multi-gigabit optic links. Four SFP+ modules service 4×9.6 Gbps uplinks and 2×4.8 Gbps downlinks, handled respectively by two re-programmable Kintex Ultrascale+ Field Programmable Gate Arrays (FPGAs) and two CERN-developed gigabit link application-specific integrated circuits (GBTx). The GBTx recovers and distributes LHC synchronized phase configurable clocks that drive the FPGAs transceivers and the Analog to Digital Converters readout. Additionally, the GBTx drives a configuration bus that propagates slow control commands to the FPGAs and allows remote access to the FPGAs JTAG chains and configuration memories. Better high-speed uplink timing and improved radiation tolerance have been achieved by migrating the previous design from the Xilinx Kintex-7 FPGAs to the Kintex Ultrascale+ architecture. The new Ultrascale+ FPGAs handle the propagation of clocks and configuration commands while formatting the readout data to be sent off-detector via GTY transceivers. The DB has a double redundant radiation tolerant design that eliminates virtually all possible single failure points, consequently only two uplinks and one downlink are required for nominal running. With the purpose of minimizing radiation-induced errors and enhance data reliability: Triple Mode Redundancy (TMR) is implemented in the FPGA firmware, Cyclic Redundancy Check error verification is used in the redundant uplinks, while Forward Error Correction is handled by each GBTx in each downlink.