Electronic system for the ALICE high rate detector upgrade

A Large Ion Collider Experiment (ALICE) is one of the four major high energy physics experiments hosted at the European nuclear research laboratory of CERN, situated in Geneva, Switzerland. CERN houses the world’s most powerful particle accelerator the Large Hadron Collider (LHC). ALICE detector uses the LHC for studying the properties of the hadronic matter at high-temperature in the constituent state of Quark-Gluon plasma (QGP). From 2023 onwards the LHC is starting its RUN3 with an increased luminosity and collision rate. ALICE is going to witnesses a massive upsurge in data volume rate with an estimated value of 3.6 TB/s. To cope with the load of the readout data distribution, a dedicated data balancing electronic system is defined called the Common Readout Unit (CRU). The CRU is at the heart of the ALICE electronic system, whose primary responsibility is to distribute trigger and timing information, to aggregate raw readout data from the sub-detectors on to few manageable links and to moderate the flow of control signals among the various sub-systems. The CRU for its multi-functional role shares a common interface connection with the major neighbourhood electronic systems, namely the Detector-Specific Read Out (DSRO) electronics, the Online-Offline (O2) computing facility and the Central Trigger Processor (CTP). Different interface standards are used for data flow at the different stages. These include the Gigabit Transceiver (GBT) optical link; the Timing, Trigger and Control over Passive Optical Networks (TTC-PON); and the Peripheral Component Interconnect Express (PCIe). The firmware for CRU is implemented on the PCIe40, an Intel® Arria® 10 FPGA based DAQ engine. The dissertation work aims at the study of the CRU design architecture and the associated firmware development for the different interface links and their behaviours. The critical among them is the interface link bridge between the GBT and the TTC-PON. The pathway between the two involves the transmission of the trigger and timing information. Detailed characterisation tests are conducted to ensure the link chain is deterministic and does not involve any point of systematic uncertainty. The link chain involves multiple transition points, hence checked for the behaviour of the stochastic noises. The interference effect of the channel noise on the timing signal as jitter is evaluated. Inline jitter cleaning PLL is used to keep the jitter within the tolerable range as allowed in the ALICE experiment. Impact of temperature variation on the PLL jitter-cleaning ability is also investigated. Apart from the detailed engineering work discussed related to the CRU development, four auxiliary developments that have branched out of the CRU design necessities are embodied in the dissertation work. Firstly, the development of a phase measurement system having resolution and precision in the range of few picoseconds is covered. The sophisticated instrumentation method developed allows the measurement of the phase value inside the FPGA itself without the requirement for other external hardware. Secondly, the need of cyclic redundancy checksum to check for the detector specific data integrity within the CRU is elaborated. The parameters of the design are runtime configurable with the ability to work on a data rate of over 10 Gbps having the processing latency of a unit clock cycle. Thirdly, is the prototype of a secure error resilient protocol having better security and resilience than other frequently used interfaces. Fourthly, a futuristic design solution termed as the Data Aggregation Unit (DAU) is proposed. The idea of DAU is as fundamental as the router itself and highlights the necessity for defining conventional standards for a data balancing block in the high energy physics experiments. In a nutshell, the dissertation discusses the journey of the ALICE detector towards RUN3 that involves the evolution of a new electronic system called the CRU. The engineering work and the other related development during the CRU hardware design implementations are covered. The dissertation closes with an idea for a futuristic design solution of a generic hardware architecture that would be suitable for upcoming mesh based readout framework and allows vertical transitions of the current CRU design.