Jets and topological trigger selection performed with the last generation Xilinx FPGA

For LHC Run3, ATLAS is planning a major detector and trigger upgrade. The new Feature EXtractors (FEXs) system will allow to reconstruct different physics objects for the Level-1 calorimeter trigger selection. This includes a Jet FEX, which will identify small/large area jets and MET. An upgraded L1...

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Detalles Bibliográficos
Autor principal: Palka, Marek
Lenguaje:eng
Publicado: 2018
Materias:
Particle Physics - Experiment
Acceso en línea:http://cds.cern.ch/record/2641447
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author Palka, Marek
author_facet Palka, Marek
author_sort Palka, Marek
collection CERN
description For LHC Run3, ATLAS is planning a major detector and trigger upgrade. The new Feature EXtractors (FEXs) system will allow to reconstruct different physics objects for the Level-1 calorimeter trigger selection. This includes a Jet FEX, which will identify small/large area jets and MET. An upgraded L1 Topological Processor will allow to select interesting physics events applying topological constraints. To achieve up to ~3 Tb/s input bandwidth and substantial processing power with tight latency budget of <390 ns, the trigger boards host up to four Ultrascale+ FPGAs. Design and test results of full-scale prototypes from integrated tests will be reported.
id cern-2641447
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2018
record_format invenio
spelling cern-26414472019-09-30T06:29:59Zhttp://cds.cern.ch/record/2641447engPalka, MarekJets and topological trigger selection performed with the last generation Xilinx FPGAParticle Physics - ExperimentFor LHC Run3, ATLAS is planning a major detector and trigger upgrade. The new Feature EXtractors (FEXs) system will allow to reconstruct different physics objects for the Level-1 calorimeter trigger selection. This includes a Jet FEX, which will identify small/large area jets and MET. An upgraded L1 Topological Processor will allow to select interesting physics events applying topological constraints. To achieve up to ~3 Tb/s input bandwidth and substantial processing power with tight latency budget of <390 ns, the trigger boards host up to four Ultrascale+ FPGAs. Design and test results of full-scale prototypes from integrated tests will be reported.ATL-DAQ-SLIDE-2018-805oai:cds.cern.ch:26414472018-10-02
spellingShingle Particle Physics - Experiment
Palka, Marek
Jets and topological trigger selection performed with the last generation Xilinx FPGA
title Jets and topological trigger selection performed with the last generation Xilinx FPGA
title_full Jets and topological trigger selection performed with the last generation Xilinx FPGA
title_fullStr Jets and topological trigger selection performed with the last generation Xilinx FPGA
title_full_unstemmed Jets and topological trigger selection performed with the last generation Xilinx FPGA
title_short Jets and topological trigger selection performed with the last generation Xilinx FPGA
title_sort jets and topological trigger selection performed with the last generation xilinx fpga
topic Particle Physics - Experiment
url http://cds.cern.ch/record/2641447
work_keys_str_mv AT palkamarek jetsandtopologicaltriggerselectionperformedwiththelastgenerationxilinxfpga

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