The Design and Testing of the Address in Real Time Data Driver Card for the Micromegas Detector of the ATLAS New Small Wheel Upgrade

The address in real-time data driver card (ADDC) is designed to transmit the trigger data in the micromesh gaseous structure (Micromegas, MM) detector of the ATLAS new small wheel (NSW) upgrade. The address in real-time (ART) signals are generated by the front-end application-specific integrated circuit (ASIC), named VMM chip, to indicate the address of the first above-threshold event. A custom ASIC (ART ASIC) is designed to receive the ART signals from the VMM chip and implement the hit selection. The processed data from the ART ASIC will be transmitted out of the NSW through the gigabit transceiver (GBTx) serializer, the unidirectional versatile twin transmitter (VTTx), and fiber-optic links. The ART signal is critical for the ATLAS experiment trigger selection; thus, the performance and stability of the ADDC is very important. To ensure extensive testing of the ADDC, a field-programmable gate array (FPGA) mezzanine card (FMC)-based testing platform and a specially designed firmware/software are developed. This test platform works with the commercial Xilinx VC707 FPGA development kit; independent of the other electronics in the NSW, it can test all the functions of the ADDC and it has long-term stability. This article will introduce the design, testing procedure, and results of the ADDC and the FMC testing platform.