Test beam and simulation studies on High Resistivity CMOS pixel sensors

The Compact Linear Collider CLIC is an option for a future electron positron collider at CERN, with a centre of mass energy up to 3 TeV. The demanding physics goals at CLIC require a lightweight silicon vertex detector and a large area silicon tracker and impose challenging requirements on both, in view of a spatial resolution of a few micrometres, a timing resolution of a few nanoseconds and a material budget less than two percent of a radiation length per layer. To reach these requirements different silicon detector technologies are under investigation. Benefiting from the small fill factor design and the resulting low sensor capacitance, as well as from the possibility to implement the readout electronics in the sensor, High Resistivity CMOS sensors are attractive in view of fast timing, low material budget and large area production. In this context, High Resistivity CMOS test chips with pixels of the size of the square of 28 micrometres have been investigated using laboratory and test beam measurements and simulations. The setup used for the measurements allows for detailed studies of the full analogue response for different process variants, pixel layouts and operation conditions. Laboratory measurements show the advantage of the small fill factor design with a low noise down to approximately 20 electrons. Corrections applied during the analysis allow for a further noise reduction down to approximately 10 electrons. Test beam measurements show that the resulting low detection threshold allows for an improvement of the position resolution through charge interpolation, down to approximately 3 micrometres for a pixel size of 28 micrometres. A timing resolution of approximately 6 nanoseconds has been measured that is limited by the test setup. For low thresholds of less than 350 electrons an efficiency larger than 99 percent has been measured. In-pixel resolved measurements have been performed to gain a better understanding of the charge sharing and charge collection for different process variants and operation conditions. An even more detailed access to the technology could be reached with finite element simulations, showing the electric field distributions and the resulting charge propagation within the sensor. The finite element simulations have been further integrated in a simulation chain that has been developed to model the response measured in test beam experiments, including noise and energy fluctuations as well as the digitisation of the charge. The simulated response is in agreement with the test beam measurements and the simulation chain has been applied to predict the spatial resolution for different digitisation parameters. Overall, the performed studies give insights into various High Resistivity CMOS process variants and pixel designs that are relevant for CLIC and other applications.