The Barrel Calorimeter Processor demonstrator board for the Phase II Upgrade of the CMS ECAL Barrel

\hspace*{0.5cm}The Phase II upgrade of the LHC is foreseen for the 2023-2025 timeline. In order to cope with increase in instantaneous luminosity from 2x10$^{34}$cm$^{-2}$s$^{-1}$ (Phase I upgrade) to 7.5x10$^{34}$cm$^{-2}$s$^{-1}$ and 200 pile-up \cite{Contardo:2020886}, the CMS electromagnetic and hadronic calorimeters in the barrel region (EB, HB) will be upgraded. For EB, the functions of the legacy front-end (FE) electronics will be moved to the upgraded back-end (BE) and expanded in order to handle the required increase in the sampling frequency and granularity of the system. On the roadmap to a final prototype hardware platform for the upgraded back-end electronics, the design of the Barrel Calorimeter Processor demonstrator board (BCPd) is presented. The BCPd has been designed as a development platform which fulfills all EB and HB functions, as well as the trigger and the data acquisition requirements. It hosts one KCU115 Kintex UltraScale FPGA and provides 56 bidirectional serial links, running any serial protocol that is synchronous or asynchronous with the LHC (40.08 MHz) within the 1Gb/s to 16Gb/s data-rate range. The target for the BCPd board is not to have a fully equipped board like the final BCP platform which will host two FPGAs, but instead to have a hardware platform flexible enough to be able to evaluate all EB functions. One of the main functions to be evaluated with BCPd board is jitter performance of the sampling clock distributed to the front-end system with respect to BCP system.