Application of FPGAs to Triggering in High Energy Physics

The High Luminosity upgrade of the LHC will increase the instantaneous luminosityto 5 × 1034 cm−2 s−1 , resulting in an increase in the number of simultaneous protonproton collisions per event (pileup) to the range 140-200. The CMS Level 1 Triggersystem will be upgraded, and will reduce the 40 MHz event rate to 750 kHz. Thesystem will perform a fast event reconstruction on FPGA devices, and select eventsfor read out within a latency of 12.5 µs.The high level FPGA programming tool MaxCompiler is investigated for usein Level 1 Trigger applications. An existing trigger algorithm, originally developedwith a Hardware Description Language, is reimplemented using MaxCompiler andcompared to the original. Bitwise agreement between the outputs is observed, withhalf as many lines of code, at the expense of some extra FPGA resources.A hardware demonstration of a proposed Level 1 track reconstruction is presented, with a Kalman Filter track fit developed with MaxCompiler. The performance of the tracking is investigated, as well as the potential for developing advancedalgorithms with low latency using the tool. A high tracking efficiency, and preciseparameter resolutions, are achieved with a 3.7 µs latency in high pileup events. Aboosted decision tree classifier, implemented with inference latency of a few clockcycles, is presented as a means to reject fake tracks.After the Level 1 Trigger, events are further processed on commodity PCs in theHigh Level Trigger (HLT). The High Luminosity LHC will also challenge the HLT,which is projected to require twenty times the processing power used during LHCRun II. Part of the HLT tracking is ported to Maxeler Dataflow Engines (DFEs),a hardware acceleration technology. A faster rate of processing is achieved, butwith an initial latency of the host-DFE communication that limits the performance.Steps which might yield acceleration are identified.