A 65 nm Data Concentration ASIC for the CMS Outer Tracker Detector Upgrade at HL-LHC

The Concentrator Integrated Circuit (CIC) ASIC is a front-end chip for both Pixel-Strip (PS) and Strip-Strip (2S) modules of the future Phase-II CMS Outer Tracker upgrade at the High Luminosity LHC (HL-LHC). It collects the digital data coming from eight upstream front-end chips (either MPAs or CBCs...

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Detalles Bibliográficos
Autores principales: Nodari, Benedetta, Caponetto, Luigi, Galbit, Geoffrey Christian, Scarfi', Simone, Viret, Sebastien
Lenguaje:eng
Publicado: 2018
Materias:
Detectors and Experimental Techniques
Acceso en línea:http://cds.cern.ch/record/2650712
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author Nodari, Benedetta
Caponetto, Luigi
Galbit, Geoffrey Christian
Scarfi', Simone
Viret, Sebastien
author_facet Nodari, Benedetta
Caponetto, Luigi
Galbit, Geoffrey Christian
Scarfi', Simone
Viret, Sebastien
author_sort Nodari, Benedetta
collection CERN
description The Concentrator Integrated Circuit (CIC) ASIC is a front-end chip for both Pixel-Strip (PS) and Strip-Strip (2S) modules of the future Phase-II CMS Outer Tracker upgrade at the High Luminosity LHC (HL-LHC). It collects the digital data coming from eight upstream front-end chips (either MPAs or CBCs, depending on the module type), formats the signal in data packets containing the trigger information from eight bunch crossings and the raw data from events passing the first trigger level, and finally transmits them to the LpGBT unit. The design and its implementation in a 65 nm CMOS technology of the first prototype that integrates all functionalities for system level operation are presented in this contribution.
id cern-2650712
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2018
record_format invenio
spelling cern-26507122022-01-14T15:03:53Zhttp://cds.cern.ch/record/2650712engNodari, BenedettaCaponetto, LuigiGalbit, Geoffrey ChristianScarfi', SimoneViret, SebastienA 65 nm Data Concentration ASIC for the CMS Outer Tracker Detector Upgrade at HL-LHCDetectors and Experimental TechniquesThe Concentrator Integrated Circuit (CIC) ASIC is a front-end chip for both Pixel-Strip (PS) and Strip-Strip (2S) modules of the future Phase-II CMS Outer Tracker upgrade at the High Luminosity LHC (HL-LHC). It collects the digital data coming from eight upstream front-end chips (either MPAs or CBCs, depending on the module type), formats the signal in data packets containing the trigger information from eight bunch crossings and the raw data from events passing the first trigger level, and finally transmits them to the LpGBT unit. The design and its implementation in a 65 nm CMOS technology of the first prototype that integrates all functionalities for system level operation are presented in this contribution.CMS-CR-2018-278oai:cds.cern.ch:26507122018-10-15
spellingShingle Detectors and Experimental Techniques
Nodari, Benedetta
Caponetto, Luigi
Galbit, Geoffrey Christian
Scarfi', Simone
Viret, Sebastien
A 65 nm Data Concentration ASIC for the CMS Outer Tracker Detector Upgrade at HL-LHC
title A 65 nm Data Concentration ASIC for the CMS Outer Tracker Detector Upgrade at HL-LHC
title_full A 65 nm Data Concentration ASIC for the CMS Outer Tracker Detector Upgrade at HL-LHC
title_fullStr A 65 nm Data Concentration ASIC for the CMS Outer Tracker Detector Upgrade at HL-LHC
title_full_unstemmed A 65 nm Data Concentration ASIC for the CMS Outer Tracker Detector Upgrade at HL-LHC
title_short A 65 nm Data Concentration ASIC for the CMS Outer Tracker Detector Upgrade at HL-LHC
title_sort 65 nm data concentration asic for the cms outer tracker detector upgrade at hl-lhc
topic Detectors and Experimental Techniques
url http://cds.cern.ch/record/2650712
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