Novel silicon detector technologies for the HL-LHC ATLAS upgrade

The Large Hadron Collider (LHC) at the European Organization for Nuclear Research (CERN), Geneva, will interrupt its operation in 2023 to be upgraded to high luminosity (HL-LHC) and provide proton-proton collisions with a center of mass energy of ${\sqrt{s} = 14 \, \mathrm{TeV}}$ at a luminosity of ${10^{35} \, \mathrm{cm^{-2}s^{-1}}}$. ATLAS, one of the two general purpose experiments at the LHC, will have to be upgraded to meet the new requirements given by the larger luminosity. Among other things the ATLAS upgrade foresees the replacement of the Inner Detector with a full silicon Inner Tracker (ITk), with finer granularity and improved radiation tolerance, and the introduction of the High Granularity Timing Detector (HGTD) that will provide timing information of tracks and vertices. Combining the measurements of ITk and HGTD it will be possible to resolve vertices close in space but separated in time, improving the ATLAS reconstruction performance. In this thesis two novel silicon detector technologies are investigated for applications in the HGTD and ITk, the Low Gain Avalanche Detectors (LGAD) and the HV-CMOS technologies. The LGAD technology consists of planar n-on-p silicon detectors with a highly doped p-type implantation underneath the n-type electrode that is designed to increase the gain of the sensor through impact ionization. It was originally developed for radiation hard tracking detectors but the fine segmentation of the electrode proved to affect the charge multiplication mechanism and no gain has been observed on segmented devices. On the other hand, thin LGAD detectors have shown a time resolution of about ${30 \, \mathrm{ps}}$ on the detection of minimum ionizing particles and it was chosen as the baseline technology for the HGTD sensors. Studies of LGAD sensors, before and after irradiation, were first performed in the context of this thesis. The HV-CMOS technology was originally aimed to provide active pixel sensors with the advantage, compared to the standard hybrid devices, of the AC coupling capability. However, during the R\&D effort, it become clear that monolithic HV-CMOS devices offered the most promising advantages: moderate radiation hardness and cost reduction. This thesis includes the characterization of the first full scale HV-CMOS chip prototype for the ATLAS experiment. This technology is currently being considered as a drop-in option for the outer layer of the ITk pixel detector.