A radiation tolerant readout link and control board for the Phase-II upgrade of the ATLAS Hadronic Tile Calorimeter

We present performance and radiation test results for the updated prototype of a radiation tolerant read-out link and control board (Daughterboard) for the Phase-II upgrade of the ATLAS Hadronic Tile Calorimeter (TileCal) front-end electronics for high-luminosity LHC. In the upgraded system, photomultiplier signals are amplified, shaped and digitized by the front-end electronics and a Mainboard (MB), while the DB collects and transmits the digitized data off-detector over multigigabit optical links. The DB provides a bi-directional interface between the front-end and off-detector electronics, receiving configuration, control and LHC-synchronous timing over two 4.8 Gbps downlinks to a pair of CERN GBTx ASICs, and providing high-speed readout off-detector over two redundant 9.6 Gbps uplinks, each driven by one of two Xilinx Kintex Ultrascale FPGAs. The DB design is double redundant to minimise single-point failure modes, and the FPGA firmware uses strategies including TMR, FEC and CRC to minimize the effects of single-event upsets and damage from hadronic and minimum ionizing radiation. The DB is expected to receive approximately 0.2 krad of total ionizing and 2.44 $\times$ 10$^{11}$ neutrons / cm$^{2}$ of non-ionising radiation over a 10 year period, so the prototype board and components have undergone TID, NIEL and SEE with large safety factors to be radiation qualified for high-luminosity LHC operations.