Development and characterisation of the Fast Timing Micro-Pattern Gaseous Detector

The work presented in this thesis concentrated on the development of the Fast Timing Micro-pattern gaseous detector (FTM), together with the tests of its dedicated electronics. The time resolution of MPGDs is mostly determined by the statistical fluctuations on the production of primary electron-ion pairs and it is limited to few ns. The FTM was developed to overcome this limit: the basic idea to improve the time resolution in a spark-protected MPGD is the segmentation of the drift gap and the use of fully resistive WELL layers. The existing FTM prototypes had different limitations and construction problems and the FTM v.4 was designed in order to overcome these problems and confirm (and extend) the results obtained with the very first FTM prototype: the new prototype has four 50 µm-thick kapton amplification structures similar to the ones used in the first prototype; on the other hand, several upgrades were implemented on the FTM v.4, such as the completely modular design, the forced gas flow through all detection layers, the front-end electronics mounted as close as possible to the readout strips, the use of high speed connectors with rugged grounding. The new FTM was assembled during the thesis at CERN and tested with x-rays in Bari. The experimental setup was validated with a Single-GEM detector used as a benchmark. An experimental procedure for the characterisation of MPGD detectors has been established. The tests showed the limitations of using x-rays for thin-drift-gap resistive detectors and the setting up of a UV laser facility has been proposed for future tests. On the other hand, the gain of a single-GEM detector has been measured with high precision and the same procedure can be exploited to test GEM detectors with different geometries, e.g. thick-GEM detectors, in order to explore alternative options for the FTM amplification layers for future prototypes. A dedicated electronics for the acquisition of small signals with good time resolution has been developed in Bari. The first version of the FAst Timing Integrated Circuit (FATIC) has been characterised and the comparison between its performances and the FTM requirements have led to improvements for the design of the second version of the chip