Building a RISC-V CPU in 5 minutes

<!--HTML-->RISC-V is a fully open source processor architecture. It’s rapidly being adopted by major tech companies as an alternative to ARM licenses. With the advent of the IceStorm toolchain for the Lattice iCE40 FPGA, it’s now possible to construct your own RISC-V processor core and compile...

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Detalles Bibliográficos
Autor principal: Devine, James
Lenguaje:eng
Publicado: 2019
Materias:
IT Lightning Talks (ITLT)
Acceso en línea:http://cds.cern.ch/record/2673990
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author Devine, James
author_facet Devine, James
author_sort Devine, James
collection CERN
description <!--HTML-->RISC-V is a fully open source processor architecture. It’s rapidly being adopted by major tech companies as an alternative to ARM licenses. With the advent of the IceStorm toolchain for the Lattice iCE40 FPGA, it’s now possible to construct your own RISC-V processor core and compile code to run on it using exclusively open source tools. This talk will include an overview of the RISC-V architecture, the toolchains for device synthesis and code compilation and will end with a very short demo of a working processor built during the talk!
id cern-2673990
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2019
record_format invenio
spelling cern-26739902022-11-02T22:13:16Zhttp://cds.cern.ch/record/2673990engDevine, JamesBuilding a RISC-V CPU in 5 minutesIT Lightning Talks: session #18IT Lightning Talks (ITLT)<!--HTML-->RISC-V is a fully open source processor architecture. It’s rapidly being adopted by major tech companies as an alternative to ARM licenses. With the advent of the IceStorm toolchain for the Lattice iCE40 FPGA, it’s now possible to construct your own RISC-V processor core and compile code to run on it using exclusively open source tools. This talk will include an overview of the RISC-V architecture, the toolchains for device synthesis and code compilation and will end with a very short demo of a working processor built during the talk!oai:cds.cern.ch:26739902019
spellingShingle IT Lightning Talks (ITLT)
Devine, James
Building a RISC-V CPU in 5 minutes
title Building a RISC-V CPU in 5 minutes
title_full Building a RISC-V CPU in 5 minutes
title_fullStr Building a RISC-V CPU in 5 minutes
title_full_unstemmed Building a RISC-V CPU in 5 minutes
title_short Building a RISC-V CPU in 5 minutes
title_sort building a risc-v cpu in 5 minutes
topic IT Lightning Talks (ITLT)
url http://cds.cern.ch/record/2673990
work_keys_str_mv AT devinejames buildingariscvcpuin5minutes
AT devinejames itlightningtalkssession18

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