Digital signal processing in FPGA for particle track reconstruction at the HL-LHC ATLAS

In the context of the high-luminosity large hadron collider (HL-LHC) upgrade, this work presents the latest update on the design of the FPGA firmware responsible of particle track reconstruction in the pattern recognition mezzanine (PRM) of the hardware-based tracking for the trigger (HTT) system, a subsystem of the ATLAS experiment trigger and data acquisition system. This computationally demanding task relies heavily on two FPGA features: the embedded in silicon digital signal processing (DSP) components and the performance of an available high bandwidth memory (HBM). These slides report the mathematical algorithm used for track reconstruction and analyses a preliminary performance test. These considerations are then used to provide estimates on the DSP and HBM resource usage in order to prove the feasibility of the firmware design. Finally, key factors for a parallel design are identified and outlook presented.