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Digital signal processing in FPGA for particle track reconstruction at the HL-LHC ATLAS
In the context of the high-luminosity large hadron collider (HL-LHC) upgrade, this work presents the latest update on the design of the FPGA firmware responsible of particle track reconstruction in the pattern recognition mezzanine (PRM) of the hardware-based tracking for the trigger (HTT) system, a...
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| Lenguaje: | eng |
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2019
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| Acceso en línea: | http://cds.cern.ch/record/2674924 |