Design, Verification and Testing of a Digital Signal Processor for Particle Detectors

The A Large Ion Collider Experiment (ALICE) at the Large Hadron Collider at CERN is upgrading two of its sub-detectors, the Time Projection Chamber and Muon Chambers, with new front-end electronics to handle the expected higher Pb–Pb collision-rates in the next running period (Run 3) foreseen to start in 2021. The higher collision rate requires the detectors to employ a continuous readout of the data from the front-end, in contrast to the previous triggered readout. The devices currently employed for the readout of the detectors can only operate in triggered mode and need to be replaced. A new 32-channel integrated circuit called SAMPA has been designed to match the requirements of both detectors. The SAMPA device contains a charge sensitive amplifier, a pulse shaper, and a 10-bit 10 MHz analogue to digital converter for each channel and a common digital signal processor part. The digital signal processor provides various signal filtering and conditioning operations to improve on the data compression ability. Acquisition can be done in either triggered or continuous mode and the data is offloaded through 320 Mbps differential serial links, allowing a data throughput of up to 3.2 Gbps. The first prototype of the SAMPA was delivered in 2014, the second in 2016 and the third was delivered in end of 2017. The final production run was done in mid-2018 and completed the testing at the end of 2018. Front-End Card production and testing is underway and the Muon Tracking Chamber (MCH) and Time Projection Chamber (TPC) are ready for installation in mid-2019. The main purpose of this thesis has been to specify, design, test and verify the digital signal processing part of the SAMPA device to encompass the needs of the detectors involved. Innovative solutions have been employed to reduce the bandwidth required by the detectors, as well as adaptations to ease data handling later in the processing chain. By means of simulations, test procedures, verification methods and applied methods for design of reliable systems, a major part of the work has been on qualifying the design for submission to production. Since the design submission process and the following production time of the device is quite long and as the only means of verifying and reading out data from the analogue front-end and the analogue to digital converter is through the digital part of the device, it is of the essence to have a complete functioning prototype of the digital design before submission. A high-speed data acquisition system was developed to enable test and verification of the produced devices. It has been used in all facets of qualification of the device for use by the detectors. Three rounds of prototypes have been produced and tested. Only minor modifications to the digital design were added between the second and third prototype. The final production of about 80 000 devices has been completed with the same design as for the third prototype. No major issues have been found in the final design. The design and test features implemented in the design have been utilized in the production testing and a final yield of close to 80 % have been reached.