Beam test studies of monolithic pixel structures for CLIC vertex detector

The Compact Linear Collider (CLIC) is an international project of e$^{+}$ e$^{−}$ linear accelerator with maximal centre-of-mass energy of 3 TeV. It is planned to be located near CERN scientific centre in Switzerland. The intensive development of both accelerator and detectors are ongoing. One of the challenging part is a vertex detector, which physics-driven requirements are highly demanding. For this detector, situated closest to an interaction point, a spatial resolution of 3 μm, time-stamping of 10 ns and material budget less than 0.2 % of radiation length per layer is foreseen. In order to reach these goals different silicon detector technologies are being tested, including monolithic solutions. Theirs benefit over hybrid technologies is that they integrate readout electronics and sensor matrix on the same wafer and bump-bonding process is no longer needed. This limits the material budget of a detector, decreasing a particle scattering. In this dissertation the test-beam data analysis results of monolithic pixel detectors designed in Japanese Fully-Depleted Low-Leakage Lapis 200 nm Silicon-On-Insulator (SOI) CMOS technology are presented. The SOI CMOS is implementing an insulator layer into standard CMOS structure and thus a substrate and thin silicon layer dedicated for electronics circuits are separated from each other. For the substrate the highly-resistive silicon wafer is used which makes the structure perfect for particle detectors. Two pixel detector prototypes targeted to fulfill the CLIC vertex detector spatial resolution requirement were designed in Cracow, fabricated in Japan and tested in CERN. The prototypes incorporate source follower and charge-sensitive preamplifier pixel readout electronics. The pixel size is 30 μm × 30 μm and the matrix consists of 16 × 36 pixels. The detectors were fabricated on different substrate types. Both systems were tested on beam at Super Proton Synchrotron (SPS) in collaboration with CLICdp group. Various analysis methods were developed in terms of the SOI pixel detector performance studies, focusing mainly on the efficiency and spatial resolution optimisation. The results indicate on a very good performance of the tested prototypes. The spatial resolution is in the best case on the level of 2.1 – 2.7 μm at the efficiency of about 96 % – 98 %. The performed studies show a high potential of the SOI CMOS technology for future devices proposed for the CLIC vertex detectors and other highly-demanding applications.