REDESIGN OF THE ATLAS TILE CALORIMETER READOUT LINK AND CONTROL BOARD FOR THE HIGH LUMINOSITY LHC ERA

The R\&D for the new on-detector electronics for the Phase-II ATLAS upgrade for the High Luminosity Large Hadron Collider (HL-LHC) has motivated progressive redesigns of the ATLAS Tile Calorimeter (TileCal) Daughterboard (DB). The DB is the readout link and control board interface to the off-detector electronics of TileCal. The DB receives configuration commands and LHC timing via two CERN radiation hard GBTx ASICs and two redundant 4.8 Gbps downlinks. Two Ultrascale+ FPGAs propagate the control to the front-end. Simultaneously, the FPGAs send continuous high-speed readout of digitized PMT samples through four 9.6 Gbps uplinks. We present a DB redesign that further improves the timing scheme, and enhances the radiation tolerance of the board by mitigating SEL induced errors and implementing a more robust power-up and current monitoring scheme. The design minimizes points of failure and reduces sensitivity to SEUs and radiation damage by employing a double-redundant scheme, using Triple Mode Redundancy (TMR) and Xilinx Soft Error Mitigation (SEM) in the FPGAs, adopting CRC error verification in the uplinks and FEC in the downlinks.