New Jet Feature Extraction and Topological Processor modules for ATLAS Phase-I trigger upgrade

For Run-3 at the Large Hadron Collider (LHC), ATLAS is planning a major detector and trigger upgrade to be installed during the long shutdown 2. As a part of this, the Level-1 trigger, based on calorimeter data, will be upgraded to exploit the fine granularity readout using a new system of Feature EXtractors (FEXs) and a new Topological Processor (L1Topo) that will process the Trigger Objects (TOBs) send by FEXs and L1Muon, selecting interesting physics events by applying topological constraints. To achieve up to ~ 3 Tb/s input bandwidth and substantial processing power with tight latency budget of < 390 ns, the trigger boards host up to four Ultrascale+ FPGAs. An overview of the architecture, simulation and test results of full-scale prototypes from integrated tests will be presented.