New pixel-detector technologies for the ATLAS ITk upgrade and the CLIC vertex detector

This thesis contains the Ph.D. work done on the characterization of novel silicon pixel detectors, based on the new HV-CMOS technology, for the ATLAS ITk upgrade and the future CLIC vertex detector. In order to provide the best precision and accuracies for the respective ATLAS and CLIC physics measurement plans, both ATLAS ITk and the CLIC vertex detectors are designed with high demanding requirements, pushing to the limits the standard technologies used for silicon pixel detectors. Current silicon pixel detectors are built using a standard planar silicon sensor coupled to a read-out chip via bump-bonds, demanding the design of two different devices and the coupling process between them, called hybridization. The new HV-CMOS technology allows implementing a sensor and read-out device in the same silicon substrate, combining the high-voltage capabilities of planar silicon sensors with the signal amplification and digitization of dedicated read-out chips, eliminating the need of the detector hybridization. The current ATLAS vertex and tracker detectors will be replaced by an all-silicon detector, covering a total area of a few hundred square meters, meaning the need of many detector modules to be designed, produced and assembled. In addition, with the higher irradiation levels to come with the High Luminosity LHC upgrade, the detector needs to have a higher radiation-hardness, while keeping the same performance of the current detector. The CLIC vertex detector, on the other hand, does not have a problem with radiation tolerance due to the nature of its electron-positron collisions. Nevertheless, to achieve the high precision physics measurements targeted, the detector module needs to be very thin (< 100 $\mu$m) and designed with small pixel sizes (25 $\mu$m), which current detector hybridization technologies are not fully capable to provide with the necessary production yield. HV-CMOS monolithic prototypes have been investigated for implementation at the outer pixel layers of the ATLAS ITk detector, helping with the detector design and production time. For the CLIC vertex detector, HV-CMOS devices are investigated for implementation as capacitively coupled pixel detector (CCPD) modules, where the hybridization between the sensor and read-out devices is done via a thin layer of a dielectric glue, instead of the expensive and complex bump-bonds. In addition, the capacitive coupling of the sensor to the read-out allows having pixel sizes smaller than what currently bump-bonding techniques can provide, contributing to the miniaturization of the pixel size and, therefore, increasing the achievable detector pointing resolution. The usage of the HV-CMOS technology is first analyzed with Finite Element simulations regarding the coupling between the sensor and read-out electronics (for CCPD prototypes), continuing with the process of detector assembly into modules and, finally, the detector module performance is tested using dedicated particle beams tests in different test-beam facilities. The UniGE FE-I4 particle telescope, necessary for the tracking of the particle beam as it goes through the prototypes, was used and improved regarding the automatization of performance measurement scans and support for different electrical and mechanical requirements of different prototypes. The capacitive coupling process was optimized using a semi-automated flip-chip machine. A planarity in the order of a few hundred μrad was achieved, with an alignment accuracy < 2 $\mu$m between the two devices. The cross-talk among multiple coupled pixel-pairs was simulated and found to be < 4% for the prototype investigated for the CLIC vertex, while an ATLAS CCPD prototype simulation, with a pixel pitch 2x larger than the CLIC prototype, resulted in a cross- coupling < 0.5%. The HV-CMOS prototypes investigated on test-been has shown good performance before and after irradiation. The fully monolithic HV-CMOS ATLAS prototype has shown a detection efficiency of 99.7% measured before irradiation, when tested with a high voltage reversed bias of 60 V and low signal threshold of about 750 electrons. After irradiation up to a dose of 10$^{15}$n$_{eq}$/cm$^{2}$, the efficiency has decreased slightly to 99.2%, with 90 V high-voltage bias and a detection threshold equivalent to 1 ̃000 electrons. The results from the different HV-CMOS detector prototypes, concerning production and performance, has indicated that the HV-CMOS technology is suitable for its application in future high-energy particle collision experiments, such as the outer layers of the ATLAS ITk upgrade as well as for the future CLIC vertex detector.