Design and simulation of a very high bandwidth data processor for the LHCb VELO Upgrade detector

After the LHCb experiment is upgraded, the detector will run at a luminosity of $2 \times 10^{33}\text{ cm}^{-2}\text{ s}^{-1}$ and a readout of 40 MHz. The upgraded VELO must maintain or improve its physics performance. To achieve this, the current sensors and electronics must be replaced, which is why a detector based on hybrid silicon sensors has been chosen. The pixel sensors will be read out by a custom developed VeloPix ASIC with a special readout scheme, optimised to cope with high data rates. A particularity of this readout system is that the data is not read out in time order. For the reconstruction of tracks to be possible data must be reordered, which will be done in the TELL40 router. The purpose of this study is analysing and simulating one of the proposed designs for the said router. The main aims of this work are assessing the quality of the available Monte-Carlo-emulated data to be used as input of the simulation, and performing the actual simulation of the router. Two different sets of emulated data were tested and a simulation of the router was performed, which served to examine the internal logic, the memory requirements and the existence or not of data losses in the router.