Data-acquisition system developments for ATLAS pixel QA and QC test toward High-Luminosity LHC

In preparation for the High luminosity LHC (HL-LHC) upgrade, the whole ATLAS inner tracker will be replaced by a new silicon detector tracker. The innermost region will be covered by silicon pixel detectors as a high density of produced particles is expected. To operate at such an environment, high-resolution sensor and high-speed readout system is required. At the moment the RD53A, the prototype of front-end readout chip, and a data-acquisition system (the YARR system) based on commercial FPGA and dedicated software for quality assurance (QA) and quality control (QC) test have been developed. Due to its high density of sensor channels, output speed from RD53A is at maximum 1.28 Gbps per line, sixteen times faster than the readout front end chip currently used in ATLAS pixel system. The data-acquisition system needs to establish communication in such high speed at QC test, to validate data-acquisition path, and to optimize the procedure for data taking at high speed. From the QC perspective this optimization allows to test large numbers of modules in parallel exploiting the DAQ lines speed reducing the time needed for tests. Another challenging point is the novel concept of readout structure planned for the operation after installation. In HL-LHC, large parts of the ATLAS DAQ system infrastructure are going to be shared among all sub detectors, using FELIX systems, while current ATLAS DAQ system are dedicated for each sub detector. This means that all processes done in the present DAQ system hardware need to be overhauled into software running on the new DAQ system. To minimize the differences between the DAQ system for operation and QC test, we introduced prototype FELIX system into the DAQ path of YARR system. In this proceeding, an established DAQ structure for QA and QC test for the new pixel detector will be introduced. And results from basic QC tests of the pixel detector with new readout chip is shown.