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Advanced HDL synthesis and SOC prototyping: RTL design using Verilog
| Autor principal: | |
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| Lenguaje: | eng |
| Publicado: |
Springer
2019
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| Materias: | |
| Acceso en línea: | http://cds.cern.ch/record/2710897 |
| _version_ | 1780965171751026688 |
|---|---|
| author | Taraate, Vaibbhav |
| author_facet | Taraate, Vaibbhav |
| author_sort | Taraate, Vaibbhav |
| collection | CERN |
| id | cern-2710897 |
| institution | Organización Europea para la Investigación Nuclear |
| language | eng |
| publishDate | 2019 |
| publisher | Springer |
| record_format | invenio |
| spelling | cern-27108972021-04-21T18:09:53Zhttp://cds.cern.ch/record/2710897engTaraate, VaibbhavAdvanced HDL synthesis and SOC prototyping: RTL design using VerilogEngineeringSpringeroai:cds.cern.ch:27108972019 |
| spellingShingle | Engineering Taraate, Vaibbhav Advanced HDL synthesis and SOC prototyping: RTL design using Verilog |
| title | Advanced HDL synthesis and SOC prototyping: RTL design using Verilog |
| title_full | Advanced HDL synthesis and SOC prototyping: RTL design using Verilog |
| title_fullStr | Advanced HDL synthesis and SOC prototyping: RTL design using Verilog |
| title_full_unstemmed | Advanced HDL synthesis and SOC prototyping: RTL design using Verilog |
| title_short | Advanced HDL synthesis and SOC prototyping: RTL design using Verilog |
| title_sort | advanced hdl synthesis and soc prototyping: rtl design using verilog |
| topic | Engineering |
| url | http://cds.cern.ch/record/2710897 |
| work_keys_str_mv | AT taraatevaibbhav advancedhdlsynthesisandsocprototypingrtldesignusingverilog |