Cargando…
Semi-formal Reformulation of Requirements for Formal Property Verification
Ambiguously specified requirements can be a source of risk for safety-critical electronic designs. Requirement specifications in natural language are subject to misinterpretation. A method is proposed that reduces the risk of misinterpretations. Requirements are reformulated into semi-formal prope...
Autores principales: | Ceesay-Seitz, Katharina, Boukabache, Hamza, Perrin, Daniel |
---|---|
Lenguaje: | eng |
Publicado: |
2020
|
Acceso en línea: | http://cds.cern.ch/record/2712787 |
Ejemplares similares
-
Formal Property Verification of the Digital Section of an Ultra-Low Current Digitizer ASIC
por: Ceesay-Seitz, Katharina, et al.
Publicado: (2021) -
A Functional Verification Methodology for Highly Parametrizable, Continuously Operating Safety-Critical FPGA Designs: Applied to the CERN RadiatiOn Monitoring Electronics (CROME)
por: Ceesay-Seitz, Katharina, et al.
Publicado: (2020) -
Formal verification - Robust and efficient code: Introduction to Formal Verification
por: ALBERTSSON, Kim
Publicado: (2016) -
Formal Verification - Robust and Efficient code: Why Formal Verification
por: ALBERTSSON, Kim
Publicado: (2016) -
Formal verification of complex properties on PLC programs
por: Darvas, D, et al.
Publicado: (2014)