MPA-SSA, design and test of a 65 nm ASIC-based system for particle tracking at HL-LHC featuring on-chip particle discrimination

Particle tracking detectors for High Energy Physics need a new readout technique to cope with the increase of the collision rate foreseen for the High Luminosity LHC upgrade. In particular, the selection of interesting physics events at the first trigger stage becomes extremely challenging at high luminosity, not only because of the rate increase, but also because the selection algorithms become inefficient in high pileup conditions. A substantial increase of latency and trigger rate provides an improvement that is not sufficient to preserve the tracking performance of the current system. A possible solution consists of using tracking information for the event selection. Given a limited bandwidth, the use of tracking information for the event selection implies that the tracker has to send out self-selected information for every event. This is the reason why front-end electronics need to perform a local data reduction. This functionality relies on the capability of continuous particle discrimination on-chip based on the transverse momentum. The high complexity of the digital logic for particle selection and the very low power requirement of $<$\,100\,mW\,/\,$\text{cm}^2$ drive the choice of a 65\,nm CMOS technology. The harsh environment, characterized by a high ionizing radiation dose of 100\,Mrad and a low temperature of around -\,30\,$^{\circ}$C, requires additional studies and technology characterization. Several architectures for particle tracking have been studied and evaluated with physics events from Monte Carlo simulations. The chosen architecture reaches an efficiency of $>$\,95\,\% in particle selection and a data reduction from $\sim$\,30\,Gbps\,/\,$\text{cm}^2$ to $\sim$\,0.7\,Gbps\,/\,$\text{cm}^2$ Two full-size and full-functionality prototypes, called MPA and SSA, have been designed, produced and tested. These two readout front-end ASICs perform binary readout of silicon modules which combine pixel and strip sensors, full-event storage with triggered readout, and continuous data selection with trigger-less readout.