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A 2D FPGA-based clustering algorithm for the LHCb silicon pixel detector running at 30 MHz
Starting from the next LHC run, the upgraded LHCb data acquisition system will read and process events at the full LHC collision rate (averaging 30 MHz) by means of a large CPU farm. In order to save the power and flexibility of CPUs for the higher level tasks, an effort is being made to address the...
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| Lenguaje: | eng |
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2020
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| Acceso en línea: | http://cds.cern.ch/record/2725831 |