Characterisation of advanced silicon pixel detector prototypes for the Inner Tracker of the ATLAS experiment for the High Luminosity LHC

In preparation of the high luminosity running of the Large Hadron Collider at CERN, the ATLAS experiment will undergo a major overhaul of its mechanical structures and sensor technologies, including their services and readout system. A novel monolithic active pixel sensor based on 180 nm technology is investigated as a possible solution for layer 4 of the ATLAS Inner Tracker’s (ITk) pixel detector. Three such chip designs are assessed through extensive laboratory measurements as well as test-beam campaigns in both unirradiated and several after doses of irradiation. Analyses focus on their suitability for operation at the LHC in the 1 × 10 15 n eq /cm 2 fluence, and 70 Mrad regime. Results show that chips possessing optimised wafer substructures in pixel corners allow for high efficiency up to the target irradiation doses. In order to perform additional measurements to show correlations between the different pixel design geometries and their effects on charge sharing, a new edge-transient current technique facility was built. Results from these measurements identified charge-sharing fractions for a range of pixel and electrode dimensions. In an effort to qualify all mechanical structure (stave) prototypes being considered for the ITk, a thermal characterisation facility was developed to identify the thermal figure of merit of all such designs being considered and to assess their suitability for the different subdetector layers they are targeting. Results obtained for all designs include the dependency of stave orientations as well as convective air-flow on the thermal figure of merit. A thermal cycling campaign was also conducted on five prototypes for failure testing. Several guidelines are proposed to enhance future characterisations of this kind. In the context of the development of 1:1 scale demonstrator models housing fully mounted sensors and thermal modules, cable saver boards were designed to allow interfacing between delicate flex cables emanating from the sensors and laboratory instrumentation. The different board designs are described along with details on their integration. Following the developments of the cable saver boards, contributions in the integration of the FELIX readout system towards its integration for the ITk are presented. These include: the redesign of a compact readout board enabling communication with up to 16 FEI4b ASICs via optical links; chip configuration and scan timing measurements; and improvements to the different configuration scans needed for FEI4b chips.