A high resolution data conversion and digital processing for high energy physics calorimeter detectors readout

The LHC accelerator complex aims to enhance its own performances with the purpose of increasing the potential for discoveries in the next years. The main objective of the HL-LHC upgrade is to enhance luminosity by a factor of 10 beyond the LHC design value in order to obtain an extensive dataset for new physics searches. The HL-LHC should be operational from 2026 and the upgrade consists of a massive improvement of both the accelerator machine and the experiments. Its development will be a significant technological challenge both in terms of hardware and software. The increase in peak luminosity will provoke unprecedented levels of event pileup and all the experiments must plan to upgrade their detectors in order to perform a better event reconstruction, to improve the performances in an harsher radiation environment, and to overcome the aging effect. This PhD activity is part of the CMS EB upgrade group effort. Indeed the custom LiTE-DTU ASIC developed at the INFN Torino belongs to the baseline choice for the upgraded VFE board. The enhanced board will allow to reduce the shaping time of the signal, mitigate the APD noise, improve the spike identification, and increase the signal information through an higher sampling rate. The LiTE-DTU ASIC has been fabricated in a 65 nm CMOS technology and has a size of 2 × 2 mm$^{2}$ . The ASIC embeds two 12-bit 160 MS/s ADCs, a PLL, and a digital architecture (DTU) dedicated to the online data selection, lossless compression and data serialization at 1.28 Gb/s. The LiTE-DTU ASIC is designed to be placed inside the experimental area, close to the detector. Therefore, considering the harsher radiation environment foreseen for Phase-2, several radiation-hard design techniques have been implemented in the design.