A new revision of the ATLAS Tile Calorimeter link Daughterboard for the HL-LHC.

The upgrade of ATLAS for the High Luminosity Large Hadron Collider (HL-LHC) has propelled gradual redesigns of the ATLAS Tile Calorimeter (TileCal) read-out link and control board (Daughterboard). The Daughterboard (DB) serves as a hub communicating the on- and off-detector electronics by means of two 4.6 Gbps downlinks and two redundant pairs of 9.6 Gbps uplinks. Two CERN radiation hard GBTx ASICs receive LHC timing and configuration commands through the downlinks and propagated to the front-end through Xilinx Kintex Ultrascale FPGAs. At the same time, the Kintex FPGAs continuously transmit redundant copies of high-speed read-out of digitized PMT samples, Detector Control System signals and monitoring data through the uplinks. The DB designs aim to progressively reduce single points of failure and improve performance and reliability of the board. Mitigation of radiation damage and Single Event Upsets (SEUs) is done by employing a double-redundant scheme, using Xilinx Soft Error Mitigation (SEM) complemented by Triple Mode Redundancy (TMR) schemes in the FPGAs, adopting Forward Error Correction (FEC) in the downlinks and using Cyclic Redundancy Check (CRC) error verification in the redundant uplinks. With the revision 6 of the DB, we present a redesign that improves radiation tolerance by mitigating Single Event Latch-up (SEL) present in the previous board iteration, features a more robust power circuitry combined with a current monitoring scheme, enhances the performance of the ADC read-out, and overall improves the timing scheme of the design.