Performance Measurements of High-Bandwidth Transmission between FPGAs and Server Computers

In the mid 2020s the ATLAS pixel detector will be replaced in preparation for the high luminosity phase of the Large Hadron Collider (HL-LHC). The readout system of the detector has to cope with an increased data rate. At the same time, ATLAS aims for implementing a large part of the functionality in software solutions on server computers rather than custom-build hardware, which is the general approach in the current system. The general interface between the front-end electronics and readout system will be given by Front End LInk eXchange (FELIX) cards which feature a powerful FPGA at their core. This thesis explores the option to communicate directly from the FELIX-FPGA with a server computer with an Ethernet connection. This approach is an alternative to the baseline solution which foresees the usage of the PCI-express bus of a rack-mounted PC to which the FELIX card is attached. The PC uses a standard network card to send the data to the server computers. The exploration of a direct communication between FPGA and the server is motivated by sparing the rack-mounted PC and the network card, allowing for rack-mounting the FELIX cards themselves. Several performance tests have been performed, characterizing the FPGA-to-server communication. Data streams of up to 10.24 Gbit/s are explored. At the receiving end, the eXpress Data Path (XDP) technology is used to route the data from the network card to memory. The results show that the assignment of the different receiving processes to particular cores of the server computer are relevant to obtain an optimal performance. Some configurations are much more performant than others, concerning package loss, loss-free package rate and achievable data rate.