DT Slice Test demonstrator results

During LS2, 4 DT Chambers (MB1 to MB4 Sector 12 Wheel +2) have been instrumented with Phase-2 on-board DT electronics (OBDT) to setup a demonstrator of the upgraded system called DT Slice Test. The OBDT streams TDC hits from the detector directly to the back-end electronics in the service cavern. These back-end electronics consists of boards hosting Virtex 7 XC7VX330T-3FFG1761E FPGAs. These boards, called AB7, run both event building and a complete version of the DT Analytical Method (AM) algorithm for Trigger Primitive generation. In the two innermost chambers, the legacy electronics have been fully replaced by the Phase-2 prototypes, while for the outermost, signals coming from a fraction of the chamber frontends are split and sent in parallel to the legacy and to the Phase-2 electronics, so an event-by-event comparison of the response of the two readout and trigger chains is possible.