ATLAS ITk Pixel Detector Overview

In this work an overview of the layout and current status of development of the ITk Pixel detector is given. For the HL-LHC upgrade the current ATLAS Inner Detector is replaced by an all-silicon system. The Pixel Detector will consist of 5 barrel layers and a number of rings, resulting in about 14 m$^2$ of instrumented area. Due to the huge non-ionising fluence (1$\times$10$^{16}$ neq/cm$^2$) and ionising dose (5 MGy), the two innermost layers, instrumented with 3D pixel sensors (L0) and 100 $\mu$m thin planar sensors (L1) will be replaced after about 5 years of operation. All hybrid detector modules will be read out by novel ASICs, implemented in 65 nm CMOS technology, with a bandwidth of up to 5 Gb/s. Data will be transmitted optically to the off-detector readout system. To save material in the servicing cables, the ASICs are serially powered. Large-scale prototyping programs are being carried out by all sub-systems.