Analytical Method (AM) for DT Trigger Primitive Generation in Phase-2

A full replacement of the muon trigger system in the CMS (Compact Muon Solenoid) detector is envisaged for operating at the maximum instantaneous luminosities expected in HL-LHC (High Luminosity Large Hadron Collider) of about 5-7.5$\times10^{34}$ cm${}^{-2}$s${}^{-1}$. Under this scenario, the new on detector electronics that is being designed for the DT (Drift Tubes) detector will forward all the chamber information at its maximum time resolution. A new trigger system based on the highest performing FPGAs is being designed and will be capable of providing precise muon reconstruction and Bunch Crossing identification. An algorithm easily portable to FPGA architecture has been designed to implement the trigger primitive generation from the DT detector. This algorithm has to reconstruct muon segments from single wire DT hits which, for a given BX, come with a spread of 400 ns due to the drift time in the cell. This algorithm provides the maximum resolution achievable by the DT chambers, bringing the hardware system closer to the offline performance capabilities. Some results comparing simulation and the first implementations in the new electronics test bench are shown.