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A massively scalable Time-to-Digital Converter with a PLL-free calibration system in a commercial 130 nm process
A 33.6 ps LSB Time-to-Digital converter was designed in 130 nm BiCMOS technology. The core of the converter is a differential 9-stage ring oscillator, based on a multi-path architecture. A novel version of this design is proposed, along with an analytical model of linearity. The model allowed us to...
| Autores principales: | , , , , , , |
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| Lenguaje: | eng |
| Publicado: |
2021
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| Materias: | |
| Acceso en línea: | https://dx.doi.org/10.1088/1748-0221/16/11/P11023 http://cds.cern.ch/record/2778450 |