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ATLAS Level-0 Endcap Muon Trigger for HL-LHC

The design of the Level-0 endcap muon trigger for the ATLAS experiment at HL-LHC and the status of the development are presented. HL-LHC is planned to start the operation in 2027 with an instantaneous luminosity of $7.5 \times 10^{34} \;\mathrm{cm^{-2}s^{-1}}$. In order to cope with the proton-proto...

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Detalles Bibliográficos
Autor principal: Mino, Yuya
Lenguaje:eng
Publicado: 2021
Materias:
Acceso en línea:http://cds.cern.ch/record/2780074
Descripción
Sumario:The design of the Level-0 endcap muon trigger for the ATLAS experiment at HL-LHC and the status of the development are presented. HL-LHC is planned to start the operation in 2027 with an instantaneous luminosity of $7.5 \times 10^{34} \;\mathrm{cm^{-2}s^{-1}}$. In order to cope with the proton-proton collision rate higher than that of LHC, the trigger and readout system needs to be replaced. The new Level-0 endcap muon trigger system is required to reconstruct muon candidates with an improved momentum resolution to suppress the trigger rate with keeping the efficiency. That can be achieved by combining the signals from various subdetectors, thin gap chambers, resistive plate chambers, micromesh gaseous detectors, and scintillator-steel hadronic calorimeters, to form more offline-like tracks. The combined muon track reconstruction was demonstrated with Monte-Carlo simulation samples produced with the condition at HL-LHC. The efficiency was estimated to be greater than 90%, a few percent higher than the current system. The trigger rate was evaluated with proton-proton collision data taken with random trigger overlaid to account for a pileup of 200, which is expected at HL-LHC. The obtained value for momentum threshold of 20 GeV, primary threshold assumed for single muon trigger, is less than 30 kHz, which constitutes less than 3% of the assumed total Level-0 trigger rate of 1 MHz. Hardware implementation is planned with ATCA blades. First prototype of the ATCA blade has a Virtex UltraScale+ (XCVU13P) FPGA with 120 pairs of transceivers, which can be used to receive detector signals, and with huge memory resources suited for track reconstruction. The track reconstruction is based on a pattern matching algorithm using the detector hits and the predefined lists of hits corresponding to tracks. The algorithm with minimal utilisation of the XCVU13P FPGA resource is a major challenge. The track reconstruction firmware for full endcap coverage was provided and the implementation was succeeded with no timing violation by optimised latch circuit locations and logic grouping among Super Logic Regions. The performance was evaluated with the hit inputs from ATLAS GEANT4 full simulation. We achieved an angular resolution of less than 4 mrad, which satisfies the requirement, with less than 40% of the XCVU13P UltraRAM resources. The results constitute an important ingredients in the development of the Level-0 endcap muon trigger for HL-LHC.