FPGA implementation of a histogram-based parent bunch-crossing identification for the Drift Tubes chambers of the CMS experiment

The first running implementation on FPGA of a histogram-based trigger primitive generator for the CMS Drift Tubes (DT) at the High Luminosity LHC (HL-LHC) is presented. This project is driven by the need to generate a trigger by processing the charge collection times, acquired by means of a TDC, and asynchronously sent to the back-end. We review the design of the bunch crossing evaluation, its implementation on FPGAs of the Xilinx UltraScale family by means of High-Level Synthesis (HLS), and the performance of a demonstrator board of such a trigger.