FPGA implementation of a histogram-based parent bunch-crossing identification for the Drift Tubes chambers of the CMS experiment

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The first running implementation on FPGA of a histogram-based trigger primitive generator for the CMS Drift Tubes (DT) at the High Luminosity LHC (HL-LHC) is presented. This project is driven by the need to generate a trigger by processing the charge collection times, acquired by means of a TDC, and...

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Autor principal: Pozzobon, Nicola
Lenguaje:eng
Publicado: 2019
Materias:
Detectors and Experimental Techniques
Acceso en línea:http://cds.cern.ch/record/2780278
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author Pozzobon, Nicola
author_facet Pozzobon, Nicola
author_sort Pozzobon, Nicola
collection CERN
description The first running implementation on FPGA of a histogram-based trigger primitive generator for the CMS Drift Tubes (DT) at the High Luminosity LHC (HL-LHC) is presented. This project is driven by the need to generate a trigger by processing the charge collection times, acquired by means of a TDC, and asynchronously sent to the back-end. We review the design of the bunch crossing evaluation, its implementation on FPGAs of the Xilinx UltraScale family by means of High-Level Synthesis (HLS), and the performance of a demonstrator board of such a trigger.
id cern-2780278
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2019
record_format invenio
spelling cern-27802782021-09-06T19:04:56Zhttp://cds.cern.ch/record/2780278engPozzobon, NicolaFPGA implementation of a histogram-based parent bunch-crossing identification for the Drift Tubes chambers of the CMS experimentDetectors and Experimental TechniquesThe first running implementation on FPGA of a histogram-based trigger primitive generator for the CMS Drift Tubes (DT) at the High Luminosity LHC (HL-LHC) is presented. This project is driven by the need to generate a trigger by processing the charge collection times, acquired by means of a TDC, and asynchronously sent to the back-end. We review the design of the bunch crossing evaluation, its implementation on FPGAs of the Xilinx UltraScale family by means of High-Level Synthesis (HLS), and the performance of a demonstrator board of such a trigger.CMS-CR-2019-192oai:cds.cern.ch:27802782019-10-08
spellingShingle Detectors and Experimental Techniques
Pozzobon, Nicola
FPGA implementation of a histogram-based parent bunch-crossing identification for the Drift Tubes chambers of the CMS experiment
title FPGA implementation of a histogram-based parent bunch-crossing identification for the Drift Tubes chambers of the CMS experiment
title_full FPGA implementation of a histogram-based parent bunch-crossing identification for the Drift Tubes chambers of the CMS experiment
title_fullStr FPGA implementation of a histogram-based parent bunch-crossing identification for the Drift Tubes chambers of the CMS experiment
title_full_unstemmed FPGA implementation of a histogram-based parent bunch-crossing identification for the Drift Tubes chambers of the CMS experiment
title_short FPGA implementation of a histogram-based parent bunch-crossing identification for the Drift Tubes chambers of the CMS experiment
title_sort fpga implementation of a histogram-based parent bunch-crossing identification for the drift tubes chambers of the cms experiment
topic Detectors and Experimental Techniques
url http://cds.cern.ch/record/2780278
work_keys_str_mv AT pozzobonnicola fpgaimplementationofahistogrambasedparentbunchcrossingidentificationforthedrifttubeschambersofthecmsexperiment

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