Readiness of the radiation tolerant link Daughterboard for the High Luminosity upgrade of the ATLAS Hadronic Calorimeter

The upgrade of the ATLAS TileCal for the HL-LHC uses a Daughterboard that serves as a hub interfacing the on-detector with the off-detector electronics. The Daughterboard design features ProASIC FPGAs, Kintex Ultrascale FPGAs and CERN GBTx ASICs. The design minimizes single points of failure and radiation damage by employing a double-redundant scheme, using TMR and Xilinx SEM strategies, adopting CRC verification in the uplinks and FEC in the downlinks, and using a dedicated SEL protection circuitry. We present a summary of the studies on the Daughterboard revision 6 performance and the radiation qualification tests of the design components.