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Hardware & FPGA firmware development in the frame of the Beam Position Monitoring (BPM) system upgrade for the Super Proton Synchrotron (SPS)

This Master Thesis described the development of hardware and firmware for “Field programmable Gate Array” (FPGA) devices in the frame of the “A Logarithmic Position System” (ALPS) project. The aim of the ALPS project is the consolidation of the Beam Position Monitoring (BPM) system in the “Super...

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Detalles Bibliográficos
Autor principal: Barros Marin, Manoel
Lenguaje:eng
Publicado: 2021
Materias:
Acceso en línea:http://cds.cern.ch/record/2783152
Descripción
Sumario:This Master Thesis described the development of hardware and firmware for “Field programmable Gate Array” (FPGA) devices in the frame of the “A Logarithmic Position System” (ALPS) project. The aim of the ALPS project is the consolidation of the Beam Position Monitoring (BPM) system in the “Super Proton Synchrotron” (SPS) project. Chapter 1 introduces the environment where the ALPS project is developed. First, a brief description of CERN, its particle accelerators and experiments. Then, it introduces the instrumentation group (SY-BI) and the section in charge of the BPM systems (SY- BI-BP). At the end of the chapter, the basic concepts of BPM are explained. Chapter 2 begins with a brief description of the SPS accelerator and its main parameters. Afterwards, the most relevant points of the ALPS project specifications are introduced, both at performance and system architecture levels Chapter 3 describes the development of the “Front-End” digital electronics of the ALPS project, both at hardware and FPGA firmware levels. At the end of the chapter, the different radiation tests carried out are explained. The purpose of the radiation tests is guaranteeing the correct operation of the digital “Front-End” electronics within the radioactive environment along the SPS accelerator. Chapter 4 describes the development of the “Back-End” electronics of the ALPS project, providing a brief description of the hardware development and mainly focusing on the FPGA firmware development. Chapter 5 briefly introduces the laboratory setups implemented in the frame of the ALPS project for calibrating the electronics systems during the development phase and testing further improvements during operational stage. Chapter 6 begins with the conclusion about the development and current status of the ALPS project. Afterwards, it presents the future plans and possible additional improvements at the time of the redaction of this Master Thesis.