The Read Out Controller ASIC for the ATLAS Experiment at LHC

The ATLAS Experiment at LHC is used for fundamental research in particle physics. For its HL-LHC TDAQ system upgrade, new ASICs were developed. The Read-Out Controller (ROC) is such an on-detector radiation-tolerant ASIC that acts as a concentrator, buffer, filter and real-time data packet processor for the new endcap muon detectors. The thesis presents its elaboration, implementation, quality assurance and control with emphasis on real-world experimental results. The IC is implemented in a 130 nm CMOS technology, resulted in a square die of 22.5 mm$^2$ with 232 pads and is packaged as $16 \times 16$ BGA. The design and its performance model were validated using custom analog and digital functional FPGA-based test setups. The digital test setup emulates the asynchronous chip context, employs optimizations and automatic clock and data synchronization and is used for mass-testing. The ROC’s operation was tested while controlled ultrafast neutron beams were incident to its die. Its tolerance to the induced SEUs was evaluated and predictions for the operating environment are made. A proposed implementation of an FPGA Integrated Logic Analyzer that mitigates the observed limitations and constraints of the existing ones is included. The ROC design passed reviews within the ATLAS Collaboration and is included in the TDAQ system.