Full-system commissioning of TGC frontend electronics for Phase-2 LHC-ATLAS

The Thin Gap Chamber (TGC) system of the LHC-ATLAS is responsible for triggering muons in the endcap region at the hardware trigger stage. The frontend system of TGC will be upgraded for HL-LHC to send binary hit-map at every bunch crossing (BC) to the backend system. Such an operation requires lots of unique challenges: correct hit BC Identification, fine-tuned clock distribution, and the capability of timing calibration. Accommodating these requirements, the primary processor board (PS board) is in charge of data processing and reception of control signals distributed by the backend. An independent control module (JATHub) will take responsibility for FPGA configuration and clock phase monitoring of the PS boards with an SoC-based design. JATHub also takes role in recovering frontend electronics for unrecoverable Single Event Upset (SEU) errors due to radiation damages. The timing calibration methodology for fine-tuning the clock phase and signal timing is migrated with highly-extended flexibility in the Phase-2 system, exploiting the experience accumulated through the construction, commissioning, and operation of the existing TGC system. System-level commissioning has been launched at KEK with prototypes of PS boards and JATHub and analogue frontend electronics of Amplifier-Shaper-Discriminator (ASD) cards. The full-chain testbed system allows us to demonstrate fundamental functionalities of Trigger, Readout, Control and Calibration: clock phase fine-tuning, signal timing calibration, and hit readout with test pulse injection to ASD cards with adjusted timing parameters.