R\&D Studies for the Atlas Tile Calorimeter Daughterboard

The ATLAS Hadronic Calorimeter Daughterboard (DB) interfaces the on-detector with the off-detector electronics. The DB features two 4.6 Gbps downlinks and two pairs of 9.6 Gbps uplinks powered by four SFP+ Optical transceivers. The downlinks receive configuration commands and LHC timing to be propagated to the front-end, and the uplinks transmit continuous high-speed readout of digitized PMT samples, detector control system and monitoring data. The design minimizes single points of failure and mitigates radiation damage by means of a double-redundant scheme. To mitigate Single Event Upset rates, Xilinx Soft Error Mitigation and Triple Mode Redundancy are used. Reliability in the high speed links is achieve by adopting Cyclic Redundancy Check in the uplinks and Forward Error Correction in the downlinks. The DB features a dedicated Single Event Latch-up protection circuitry that power-cycles the board in the case of any over-current event avoiding any possible hardware damages. We present a summary of the studies performed to verify the reliability if the performance of the DB revision 6, and the radiation qualification tests of the components used for the design.