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Formal Property Verification of the Digital Section of an Ultra-Low Current Digitizer ASIC

This paper details our experience with Formal Property Verification (FPV) of the digital section of a mixed-signal Application Specific Integrated Circuit (ASIC) for ultra-low current measurements. The ASIC was developed as a prototype front-end for the future version of the CERN RadiatiOn Monitorin...

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Detalles Bibliográficos
Autores principales:	Ceesay-Seitz, Katharina, Kundumattathil Mohanan, Sarath, Boukabache, Hamza, Perrin, Daniel
Lenguaje:	eng
Publicado:	2021
Acceso en línea:	http://cds.cern.ch/record/2789695

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