Hardware Design of the Generic Rear Transition Module for the Global Trigger System of the ATLAS Phase II Upgrade

The High-Luminosity Large Hadron Collider (HL-LHC) is expected to start operations in the middle of 2027, to deliver more than ten times the integrated luminosity of the LHC Runs 1-3 combined (up to 4000 fb−1). Meeting these requirements poses significant challenges to the hardware design of the Trigger and Data Acquisition (TDAQ) system. Global Trigger is a new subsystem in the ATLAS Phase-II upgrade, which will bring event filter-like capability to the Level-0 trigger system. A common hardware platform in Advanced Telecommunications Computing Architecture (ATCA) form factor named Global Common Module (GCM) is proposed to be configured as processor nodes in the Global Trigger. To mitigate the risk and simplify the GCM hardware design, a Generic Rear Transition Module (GRM) is being developed. GRM, which has been implemented with a Xilinx Versal Prime FPGA and sufficient multi-gigabit transceivers, aims at system control and communication with the Front-End Link eXchange (FELIX). It could also provide additional processing or readout capacity.