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A radiation tolerant clock generator for the CMS Endcap Timing Layer readout chip
We present the test results of a low jitter Phase Locked Loop (PLL) prototype chip for the CMS Endcap Timing Layer readout chip (ETROC). This chip is based on the improved version of a clock synthesis circuit named ljCDR from the Low-Power Gigabit Transceiver (lpGBT) project. The ljCDR is tested in...
| Autores principales: | , , , , , , , , , , , , , , , , |
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| Lenguaje: | eng |
| Publicado: |
2021
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| Materias: | |
| Acceso en línea: | https://dx.doi.org/10.1088/1748-0221/17/03/C03038 http://cds.cern.ch/record/2790445 |
| _version_ | 1780972250377224192 |
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| author | Sun, H. Sun, Q. Biereigel, S. Francisco, R. Gong, D. Huang, G. Huang, X. Kulis, S. Leroux, P. Liu, C. Liu, T. Moreira, P. Prinzie, J. Wu, J. Ye, J. Zhang, L. Zhang, W. Liu, T. |
| author_facet | Sun, H. Sun, Q. Biereigel, S. Francisco, R. Gong, D. Huang, G. Huang, X. Kulis, S. Leroux, P. Liu, C. Liu, T. Moreira, P. Prinzie, J. Wu, J. Ye, J. Zhang, L. Zhang, W. Liu, T. |
| author_sort | Sun, H. |
| collection | CERN |
| description | We present the test results of a low jitter Phase Locked Loop (PLL) prototype chip for the CMS Endcap Timing Layer readout chip (ETROC). This chip is based on the improved version of a clock synthesis circuit named ljCDR from the Low-Power Gigabit Transceiver (lpGBT) project. The ljCDR is tested in its PLL mode. An automatic frequency calibration (AFC) block with the Triple Modular Redundancy (TMR) register is developed for the LC-oscillator calibration. The chip was manufactured in a 65 nm CMOS process with 10 metal layers. The chip has been extensively tested, including Total Ionizing Dose (TID) testing up to 300 Mrad and Single Event Upset (SEU) testing with heavy ions possessing a Linear energy transfer (LET) from 1.3 to 62.5 MeV*cm^2/mg. |
| id | cern-2790445 |
| institution | Organización Europea para la Investigación Nuclear |
| language | eng |
| publishDate | 2021 |
| record_format | invenio |
| spelling | cern-27904452023-01-31T09:05:54Zdoi:10.1088/1748-0221/17/03/C03038http://cds.cern.ch/record/2790445engSun, H.Sun, Q.Biereigel, S.Francisco, R.Gong, D.Huang, G.Huang, X.Kulis, S.Leroux, P.Liu, C.Liu, T.Moreira, P.Prinzie, J.Wu, J.Ye, J.Zhang, L.Zhang, W.Liu, T.A radiation tolerant clock generator for the CMS Endcap Timing Layer readout chipParticle Physics - ExperimentDetectors and Experimental TechniquesWe present the test results of a low jitter Phase Locked Loop (PLL) prototype chip for the CMS Endcap Timing Layer readout chip (ETROC). This chip is based on the improved version of a clock synthesis circuit named ljCDR from the Low-Power Gigabit Transceiver (lpGBT) project. The ljCDR is tested in its PLL mode. An automatic frequency calibration (AFC) block with the Triple Modular Redundancy (TMR) register is developed for the LC-oscillator calibration. The chip was manufactured in a 65 nm CMOS process with 10 metal layers. The chip has been extensively tested, including Total Ionizing Dose (TID) testing up to 300 Mrad and Single Event Upset (SEU) testing with heavy ions possessing a Linear energy transfer (LET) from 1.3 to 62.5 MeV*cm^2/mg.arXiv:2110.12625FERMILAB-CONF-21-633-PPDoai:cds.cern.ch:27904452021-10-24 |
| spellingShingle | Particle Physics - Experiment Detectors and Experimental Techniques Sun, H. Sun, Q. Biereigel, S. Francisco, R. Gong, D. Huang, G. Huang, X. Kulis, S. Leroux, P. Liu, C. Liu, T. Moreira, P. Prinzie, J. Wu, J. Ye, J. Zhang, L. Zhang, W. Liu, T. A radiation tolerant clock generator for the CMS Endcap Timing Layer readout chip |
| title | A radiation tolerant clock generator for the CMS Endcap Timing Layer readout chip |
| title_full | A radiation tolerant clock generator for the CMS Endcap Timing Layer readout chip |
| title_fullStr | A radiation tolerant clock generator for the CMS Endcap Timing Layer readout chip |
| title_full_unstemmed | A radiation tolerant clock generator for the CMS Endcap Timing Layer readout chip |
| title_short | A radiation tolerant clock generator for the CMS Endcap Timing Layer readout chip |
| title_sort | radiation tolerant clock generator for the cms endcap timing layer readout chip |
| topic | Particle Physics - Experiment Detectors and Experimental Techniques |
| url | https://dx.doi.org/10.1088/1748-0221/17/03/C03038 http://cds.cern.ch/record/2790445 |
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