A radiation tolerant clock generator for the CMS Endcap Timing Layer readout chip

We present the test results of a low jitter Phase Locked Loop (PLL) prototype chip for the CMS Endcap Timing Layer readout chip (ETROC). This chip is based on the improved version of a clock synthesis circuit named ljCDR from the Low-Power Gigabit Transceiver (lpGBT) project. The ljCDR is tested in...

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Detalles Bibliográficos
Autores principales: Sun, H., Sun, Q., Biereigel, S., Francisco, R., Gong, D., Huang, G., Huang, X., Kulis, S., Leroux, P., Liu, C., Liu, T., Moreira, P., Prinzie, J., Wu, J., Ye, J., Zhang, L., Zhang, W.
Lenguaje:eng
Publicado: 2021
Materias:
Particle Physics - Experiment
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.1088/1748-0221/17/03/C03038
http://cds.cern.ch/record/2790445

Internet

https://dx.doi.org/10.1088/1748-0221/17/03/C03038
http://cds.cern.ch/record/2790445

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